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40-channel, 14-bit, parallel and serial input, bipolar voltage-output dac ad5379 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 40-channel dac in 13 mm 13 mm 108-lead cspbga guaranteed monotonic to 14 bits buffered voltage outputs output voltage span of 3.5 v v ref (+) maximum output voltage span of 17.5 v system calibration function allowing user-programmable offset and gain pseudo differential outputs relative to refgnd clear function to user-defined refgnd ( clr pin) simultaneous update of dac outputs ( ldac pin) dac increment/decrement mode channel grouping and addressing features interface options: parallel interface dsp/microcontroller-compatible 3-wire serial interface 2.5 v to 5.5 v jedec-compliant digital levels sdo daisy-chaining option power-on reset digital reset ( reset pin and soft reset function) applications level setting in automatic test equipment (ate) variable optical attenuators (voa) optical switches industrial control systems functional block diagram v cc v dd v ss agnd reset power-on reset dgnd ldac v bias v ref 1(+) v ref 1(?) refgnd a1 vbias dac 0?1 dac reg 0?1 dac reg 2 dac reg 7 dac reg 8?9 input reg 0?1 input reg 2 input reg 7 input reg 8?9 dac 2 dac 7 dac 8?9 ad5379 dcen/wr sync/cs reg0 reg1 db13 sclk/db12 din/db11 db0 a7 a0 ser/par din sclk sdo fifoen refgnd b1 refgnd b2 refgnd c1 refgnd c2 refgnd d1 refgnd d2 busy v ref 2(+) v ref 2(?) refgnd a2 clr vout 0 vout 1 vout 2 vout 3 vout 4 vout 5 vout 6 vout 7 vout 8 vout 9 vout 10 vout 39 4 14 / 14 / 14 / 14 / 14 / 14 / 14 / 14 / 14 / 14 / 14 / 14 / 14 / 14 / m reg0?1 c reg0?1 m reg2 c reg2 m reg7 c reg7 m reg8?9 c reg8?9 14 / 14 / 14 / 14 / 14 / 14 / 14 / fifo state machine interface 03165-prt-001 figure 1. ad5379protected by u.s. patent no. 5,969,657; other pa tents pending.
ad5379 rev. 0 | page 2 of 28 table of contents general description ..........................................................................3 specifications......................................................................................4 ac characteristics........................................................................ 5 timing characteristics......................................................................6 serial interface .............................................................................. 6 parallel interface ........................................................................... 9 absolute maximum ratings...........................................................11 esd caution................................................................................ 11 pin configuration and function descriptions............................12 terminology .....................................................................................15 typical performance characteristics ............................................16 functional description ...................................................................18 dac architecturegeneral..................................................... 18 channel groups.......................................................................... 18 transfer function ....................................................................... 18 v bias function ............................................................................. 19 reference selection .................................................................... 19 calibration................................................................................... 20 clear function ............................................................................ 20 busy and ldac functions...................................................... 20 fifo vs. non-fifo operation ............................................... 21 busy input function ................................................................ 21 power-on reset function ......................................................... 21 reset input function .............................................................. 21 increment/decrement function .............................................. 21 interfaces...........................................................................................22 parallel interface......................................................................... 22 serial interface ............................................................................ 22 data decoding .................................................................................24 address decoding ...........................................................................25 power supply decoupling ..............................................................26 typical application circuit ............................................................27 outline dimensions ........................................................................28 ordering guide .......................................................................... 28 revision history revision 0: initial version
ad5379 rev. 0 | page 3 of 28 general description the ad5379 contains 40, 14-bit dacs in one cspbga package. the ad5379 provides a bipolar output range determined by the voltages applied to the v ref (+) and v ref (?) inputs. the maximum output voltage span is 17.5 v, corresponding to a bipolar output range of ?8.75 v to +8.75 v, and is achieved with reference voltages of v ref (?) = ?3.5 v and v ref (+) = +5 v. the ad5379 offers guaranteed operation over a wide v ss /v dd supply range from 11.4 v to 16.5 v. the output amplifier headroom requirement is 2.5 v operating with a load current of 1.5 ma and 2 v operating with a load current of 0.5 ma. the ad5379 contains a double-buffered parallel interface in which 14 data bits are loaded into one of the input registers under the control of the wr , cs , and dac channel address pins, a0 to a7. it also has a 3-wire serial interface, which is compatible with spi?, qspi?, microwire?, and dsp interface standards and can handle clock speeds of up to 50 mhz. the dac outputs are updated on reception of new data into the dac registers. all the outputs can be updated simultaneously by taking the ldac input low. each channel has a program- mable gain and an offset adjust register. each dac output is gained and buffered on-chip with respect to an external refgnd input. the dac outputs can also be switched to refgnd via the clr pin. table 1. high channel count, low voltage single-supply dacs model resolution av dd range output channels linearity error (lsb) package description package option ad5380bst-5 14 bits 4.5 v to 5.5 v 40 4 100-lead lqfp st-100 ad5380bst-3 14 bits 2.7 v to 3.6 v 40 4 100-lead lqfp st-100 ad5381bst-5 12 bits 4.5 v to 5.5 v 40 1 100-lead lqfp st-100 ad5381bst-3 12 bits 2.7 v to 3.6 v 40 1 100-lead lqfp st-100 ad5384bbc-5 14 bits 4.5 v to 5.5 v 40 4 100-lead cspbga bc-100 ad5384bbc-3 14 bits 2.7 v to 3.6 v 40 4 100-lead cspbga bc-100 ad5382bst-5 14 bits 4.5 v to 5.5 v 32 4 100-lead lqfp st-100 ad5382bst-3 14 bits 2.7 v to 3.6 v 32 4 100-lead lqfp st-100 ad5383bst-5 12 bits 4.5 v to 5.5 v 32 1 100-lead lqfp st-100 ad5383bst-3 12 bits 2.7 v to 3.6 v 32 1 100-lead lqfp st-100 ad5390bst-5 14 bits 4.5 v to 5.5 v 16 3 52-lead lqfp st-52 ad5390bcp-5 14 bits 4.5 v to 5.5 v 16 3 64-lead lfcsp cp-64 ad5390bst-3 14 bits 2.7 v to 3.6 v 16 3 52-lead lqfp st-52 ad5390bcp-3 14 bits 2.7 v to 3.6 v 16 3 64-lead lfcsp cp-64 ad5391bst-5 12 bits 4.5 v to 5.5 v 16 1 52-lead lqfp st-52 ad5391bcp-5 12 bits 4.5 v to 5.5 v 16 1 64-lead lfcsp cp-64 ad5391bst-3 12 bits 2.7 v to 3.6 v 16 1 52-lead lqfp st-52 ad5391bcp-3 12 bits 2.7 v to 3.6 v 16 1 64-lead lfcsp cp-64 ad5392bst-5 14 bits 4.5 v to 5.5 v 8 3 52-lead lqfp st-52 ad5392bcp-5 14 bits 4.5 v to 5.5 v 8 3 64-lead lfcsp cp-64 ad5392bst-3 14 bits 2.7 v to 3.6 v 8 3 52-lead lqfp st-52 ad5392bcp-3 14 bits 2.7 v to 3.6 v 8 3 64-lead lfcsp cp-64
ad5379 rev. 0 | page 4 of 28 specifications v cc = 2.7 v to 5.5 v; v dd = 11.4 v to 16.5 v; v ss = ?11.4 v to ?16.5 v; v ref (+) = 5 v; v ref (?) = ?3.5 v; agnd = dgnd = refgnd = 0 v; v bias = 5 v; c l = 200 pf to gnd; r l = 11 k? to 3 v; gain = 1; offset = 0 v; all specifications t min to t max , unless otherwise noted. table 2. parameter a version 1 unit test conditions/comments 2 accuracy resolution 14 bits relative accuracy 3 lsb max ?40c to +85c. 2.5 lsb max 0c to 70c. differential nonlinearity ?1/+1.5 lsb max guarant eed monotonic by design over temperature. zero-scale error 12 mv max ?40c to +85c. 5 mv max 0c to 70c. full-scale error 12 mv max ?40c to +85c. 8 mv max 0c to 70c. gain error 8 mv max ?40c to +85c. 1/5 mv typ/max 0c to 70c. vout temperature coefficient 5 ppm fs r/c typ includes linearity, offset , and gain drift. see figure 11. dc crosstalk 2 0.5 mv max typically 100 v. reference inputs 2 v ref (+) dc input impedance 1 m? min typically 100 m?. v ref (?) dc input impedance 8 k? min typically 12 k?. v ref (+) input current 10 a max per input. typically 30 na. v ref (+) range 1.5/5 v min/max 2% for specified operation. v ref (?) range ?3.5/0 v min/max 2% for specified operation. refgnd inputs 2 dc input impedance 80 k? min typically 120 k?. input range 0.5 v min/max output characteristics 2 output voltage range v ss + 2/ v ss + 2.5 v min i load = 0.5 ma/ 1.5 ma. v dd ? 2/ v dd ? 2.5 v max i load = 0.5 ma/ 1.5 ma. short circuit current 15 ma max load current 1.5 ma max capacitive load 2200 pf max dc output impedance 1 ? max digital inputs jedec compliant. input high voltage 1.7 v min v cc = 2.7 v to 3.6 v. 2.0 v min v cc = 3.6 v to 5.5 v. input low voltage 0.8 v max v cc = 2.7 v to 5.5 v. input current (with pull-up/pull-down) 8 a max ser/par , fifoen, and reset pins only. input current (no pull-up/pull-down) 1 a max all other digital input pins. input capacitance 2 10 pf max digital outputs (busy , sdo) output low voltage 0.5 v max sinking 200 a. output high voltage (sdo) v cc ? 0.5 v min sourcing 200 a. high impedance leakage current ?70 a max sdo only. high impedance output capacitance 2 10 pf typ
ad5379 rev. 0 | page 5 of 28 parameter a version 1 unit test conditions/comments 2 power requirements v cc 2.7/5.5 v min/max v dd 8.5/16.5 v min/max v ss ?3/?16.5 v min/max power supply sensitivity 2 ? full scale/? v dd ?75 db typ ? full scale/? v ss ?75 db typ ? full scale/? v cc ?90 db typ i cc 5 ma max v cc = 5.5 v, v ih = v cc , v il = gnd. i dd 28 ma max outputs unloaded. typically 20 ma. i ss 23 ma max outputs unloaded. typically 15 ma. power dissipation power dissipation unloaded (p) 850 mw max v dd = 16.5 v, v ss = ?16.5 v. power dissipation loaded (p total ) 2000 mw max p total = p + (v dd ? v o ) i source + (v o ? v ss ) i sink . junction temperature 130 c max t j = t a + p total j . 3 1 temperature range for a version: ?40c to +85c. typical specifications are at 25c. 2 guaranteed by design and characterization, not production tested. 3 where j represents the pack age thermal impedance. ac characteristics v cc = 2.7 v to 5.5 v; v dd = 11.4 v to 16.5 v; v ss = ?11.4 v to ?16.5 v; v ref (+) = 5 v; v ref (?) = ?3.5 v; agnd = dgnd = refgnd = 0 v; v bias = 5 v; c l = 220 pf; r l = 11 k ? to 3 v; gain = 1; offset = 0 v. table 3. parameter a version 1 unit test conditions/comments dynamic performance output voltage settling time 20 s typ full-scale change to 1/2 lsb. 30 s max dac latch contents altern ately loaded with all 0s and all 1s. slew rate 1 v/s typ digital-to-analog glitch energy 20 nv-s typ glitch impulse peak amplitude 15 mv max channel-to-channel isolation 100 db typ v ref (+) = 2 v p-p, (1 v bias ) 1 khz, v ref (?) = ?1 v. dac-to-dac crosstalk 40 nv-s typ see the termin ology section. between dacs inside a group. 10 nv-s typ between dacs from different groups. digital crosstalk 0.1 nv-s typ digital feedthrough 1 nv-s typ effect of in put bus activity on dac output under test. output noise spectral de nsity @ 1 khz 350 nv/(hz) 1/2 typ v ref (+) = v ref (?) = 0 v. 1 guaranteed by design and characterization, not production tested.
ad5379 rev. 0 | page 6 of 28 timing characteristics serial interface v cc = 2.7 v to 5.5 v; v dd = 11.4 v to 16.5 v; v ss = ?11.4 v to ?16.5 v; v ref (+) = 5 v; v ref (?) = ?3.5 v; agnd = dgnd = refgnd = 0 v; v bias = 5 v, fifoen = 0 v; all specifications t min to t max , unless otherwise noted. table 4. parameter 1, 2, 3 limit at t min , t max unit description t 1 20 ns min sclk cycle time. t 2 8 ns min sclk high time. t 3 8 ns min sclk low time. t 4 10 ns min sync falling edge to sclk falling edge setup time. t 5 4 15 ns min 24th sclk falling edge to sync falling edge. t 6 4 25 ns min minimum sync low time. t 7 10 ns min minimum sync high time. t 8 5 ns min data setup time. t 9 4.5 ns min data hold time. t 10 4, 5 30 ns max 24th sclk falling edge to busy falling edge. t 11 330 ns max busy pulse width low (single-channel update.) see table 10. t 12 4 20 ns min 24th sclk falling edge to ldac falling edge. t 13 20 ns min ldac pulse width low. t 14 150 ns typ busy rising edge to dac output response time. t 15 0 ns min busy rising edge to ldac falling edge. t 16 100 ns min ldac falling edge to dac output response time. t 17 20/30 s typ/max dac output settling time. t 18 10 ns min clr pulse width low. t 19 350 ns max clr /reset pulse activation time. t 20 6, 7 25 ns max sclk rising edge to sdo valid. t 21 7 5 ns min sclk falling edge to sync rising edge. t 22 7 5 ns min sync rising edge to sclk rising edge. t 23 7 20 ns min sync rising edge to ldac falling edge. t 24 5 30 ns min sync rising edge to busy falling edge. t 25 10 ns min reset pulse width low. t 26 120 s max reset time indicated by busy low. 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of v cc ) and timed from a voltage level of 1.2 v. 3 see figure 4 and figure 5. 4 standalone mode only. 5 this is measured with the load circuit of figure 2. 6 this is measured with the load circuit of figure 3. 7 daisy-chain mode only. to output pin v cc v ol c l 50pf r l 2.2k ? 03165-prt-002 figure 2. load circuit for busy timing diagram 2 v oh (min) + v ol (max) 200 a 200 a i ol i oh c l 50pf to output pin 03165-prt-003 figure 3. load circuit for sdo timing diagram (serial interface, daisy-chain mode)
ad5379 rev. 0 | page 7 of 28 busy ldac 1 vout 1 din sclk ldac 2 vout 2 clr vout 1 ldac active during busy 2 ldac active after busy reset vout busy sync t 10 t 11 t 6 t 4 t 7 t 8 t 9 db23 db0 t 3 t 1 1 2 24 24 t 2 t 5 t 12 t 13 t 14 t 17 t 13 t 16 t 18 t 19 t 25 t 19 t 26 t 17 t 15 03165-prt-005 figure 4. serial interface timing diagram (standalone mode)
ad5379 rev. 0 | page 8 of 28 03165-prt-006 sclk sync din sdo ldac busy input word for dac n input word for dac n undefined input word for dac n+1 t 24 t 11 t 13 t 23 t 21 t 22 t 20 t 8 t 9 t 4 t 7 t 3 t 2 t 1 d23 d0 d0 d0' d23' d23 24 48 figure 5. serial interface timing diagram (daisy-chain mode)
ad5379 rev. 0 | page 9 of 28 parallel interface v cc = 2.7 v to 5.5 v; v dd = 11.4 v to 16.5 v; v ss = ?11.4 v to ?16.5 v; agnd = dgnd = dutgnd = 0 v; v ref (+) = 5 v; v ref ( ? ) = ? 3.5 v, fifoen = 0 v; all specifications t min to t max , unless otherwise noted. table 5. parameter 1, 2, 3 limit at t min to t max unit description t 0 4.5 ns min reg0, reg1, address to wr rising edge setup time. t 1 4.5 ns min reg0, reg1, address to wr rising edge hold time. t 2 10 ns min cs pulse width low. t 3 10 ns min wr pulse width low. t 4 0 ns min cs to wr falling edge setup time. t 5 0 ns min wr to cs rising edge hold time. t 6 4.5 ns min data to wr rising edge setup time. t 7 4.5 ns min data to wr rising edge hold time. t 8 20 ns min wr pulse width high. t 9 240 ns min minimum wr cycle time (single-channel write). t 10 4 0/30 ns min/max wr rising edge to busy falling edge. t 11 4 330 ns max busy pulse width low (single-channel update). see table 10. t 12 0 ns min busy rising edge to wr rising edge. t 13 30 ns min wr rising edge to ldac falling edge. t 14 20 ns min ldac pulse width low. t 15 4 150 ns typ busy rising edge to dac output response time. t 16 20 ns min ldac rising edge to wr rising edge. t 17 0 ns min busy rising edge to ldac falling edge. t 18 100 ns typ ldac falling edge to dac output response time. t 19 20/30 s typ/ max dac output settling time. t 20 10 ns min clr pulse width low. t 21 350 ns max clr /reset pulse activation time. t 22 10 ns min reset pulse width low. t 23 120 s max reset time indicated by busy low. 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of v cc ) and timed from a voltage level of 1.2 v. 3 see figure 6. 4 measured with load circuit in figure 2.
ad5379 rev. 0 | page 10 of 28 reg0, reg1, a7?a02 cs wr db12?db0 busy ldac 1 vout 1 ldac 2 vout 2 clr vout 1 ldac active during busy 2 ldac active after busy reset vout busy t 0 t 1 t 4 t 5 t 2 t 3 t 9 t 8 t 6 t 7 t 16 t 10 t 11 t 13 t 14 t 12 t 15 t 19 t 14 t 18 t 20 t 21 t 22 t 21 t 23 t 19 t 17 03165-prt-004 figure 6. parallel interface timing diagram
ad5379 rev. 0 | page 11 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 6. parameter rating v dd to agnd ?0.3 v to +17 v v ss to agnd ?17 v to +0.3 v v cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to v cc + 0.3 v digital outputs to dgnd ?0.3 v to v cc + 0.3 v v ref 1(+), v ref 2(+) to agnd ?0.3 v to +7 v v ref 1(?), v ref 2(?) to agnd v ss ? 0.3 v to v dd + 0.3 v v bias to agnd ?0.3 v to +7 v vout0Cvout39 to agnd v ss ? 0.3 v to v dd + 0.3 v refgnd to agnd v ss ? 0.3 v to v dd + 0.3 v agnd to dgnd ?0.3 v to +0.3 v operating temperature range (t a ) industrial (a version) ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c 108-lead cspbga package ja thermal impedance 37.5c/w jc thermal impedance 8.5c/w reflow soldering peak temperature 230c time at peak temperature 10 s to 40 s stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5379 rev. 0 | page 12 of 28 pin configuration and fu nction descriptions 123456789101112 123456789101112 a b c d e f g h j k l m a b c d e f g h j k l m ad5379 top view 03165-prt-007 figure 7. pin configuration table 7. 108-lead cspbga ball configuration cspbga number ball name a1 reg0 a2 v cc 3 a3 db10 a4 agnd4 a5 v bias a6 vout5 a7 agnd3 a8 refgnda1 a9 v dd 5 a10 v ss 5 a11 v ss 4 a12 v dd 4 b1 reg1 b2 dgnd4 b3 db9 b4 clr b5 vout7 b6 vout6 b7 vout0 b8 vout1 b9 vout2 b10 vout31 b11 refgndd1 b12 vout30 c1 db13 c2 db12/sclk c3 db11/din cspbga number ball name c4 ser/ par 1 c5 ldac c6 vout8 c7 vout3 c8 vout4 c9 vout9 c10 vout34 c11 vout32 c12 vout33 d1 db7 d2 db8 d3 dgnd1 d10 v ref 1(?) d11 vout35 d12 vout36 e1 db5 e2 db6 e3 v cc 1 e10 refgndb2 e11 vout37 e12 vout38 f1 db4 f2 db3 f3 db2 f10 v dd 3 f11 refgndd2 f12 vout39 cspbga number ball name g1 db1 g2 db0 g3 busy g10 v ss 3 g11 vout29 g12 refgndc2 h1 wr /dcen h2 sdo 3 h3 cs / sync h10 vout28 h11 vout26 h12 vout27 j1 a0 j2 a1 j3 a2 j10 vout19 j11 vout24 j12 vout25 k1 a4 k2 a5 k3 a3 k4 dgnd2 k5 refgnda2 k6 v ref 2(?) k7 vout12 k8 vout13 k9 vout16 cspbga number ball name k10 vout18 k11 vout22 k12 vout23 l1 a7 l2 a6 l3 n/c 2 l4 reset 3 l5 vout17 l6 agnd2 l7 vout14 l8 vout10 l9 v dd 1 l10 v ref 2(+) l11 vout20 l12 vout21 m1 dgnd3 m2 v cc 2 m3 fifoen 1 m4 agnd1 m5 vout15 m6 vout11 m7 refgndb1 m8 v ref 1(+) m9 v ss 1 m10 v ss 2 m11 v dd 2 m12 refgndc1 1 internal 1 m? pull-down device on this logic input. therefore, it can be left floating and defaults to a logic low condition. 2 n/cdo not connect to this pin. internal active pull-up device on these logic inputs. they default to a logic high condition. 3 internal 1 m? pull-up device on this logic input. therefore, it can be left floating and defaults to a logic high condition.
ad5379 rev. 0 | page 13 of 28 table 8. pin function descriptions pin function v cc (1C3) logic power supply; 2.7 v to 5.5 v. these pins should be decoupled with 0.1 f ce ramic capacitors and 10 f capacitors. v ss (1C5) negative analog power supply; ?11.4 v to ?16.5 v for specified performance. th ese pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. v dd (1C5) positive analog power supply; +11.4 v to +16.5 v for specified performance. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. agnd(1C4) ground for all analog circuitry. all agnd pins should be connected to the agnd plane. dgnd(1C4) ground for all digital circuitry. all dgn d pins should be connected to the dgnd plane. v ref 1(+), v ref 1(?) reference inputs for dacs 0 to 7, 10 to 17, 20 to 27, and 30 to 37. these voltages are referred to agnd. v ref 2(+), v ref 2(?) reference inputs for dacs 8, 9, 18, 19, 28, 29, 38, and 39. these refe rence voltages are referred to agnd. v bias dac bias voltage input/output. this pin provides an access to the on-chip voltage generator voltage and is provided for bypassing and overdriving purposes only. if v ref (+) > 4.25 v, v bias must be pulled high externally to an equal or higher potential (for example, 5 v). if v ref (+) < 4.25 v, the on-chip bias generato r can be used. in this case, the v bias pin should be decoupled with a 10 nf capacitor to agnd. vout0 to vout39 dac outputs. buffered analog o utputs for each of the 40 dac channels. each analog output is capable of driving an output load of 5 k? to ground. typical o utput impedance of these amplifiers is 1 ?. ser/par interface select input. this pin allows the user to select whet her the serial or parallel interface is used. this pin has an internal 1 m? pull-down resistor, meaning that the default state at power-on is para llel mode. if this pin is tied high, the serial interface is used. sync 1 active low input. this is the frame synchron ization signal for the serial interface. sclk 1 serial clock input. data is cl ocked into the shift register on the falling ed ge of sclk. this pin operates at clock speeds up to 50 mhz. din 1 serial data input. data must be valid on the falling edge of sclk. sdo 1 serial data output. cmos output. sdo ca n be used for daisy-chaining a number of devices together. data is clocked out on sdo on the rising edge of sclk an d is valid on the falling edge of sclk. dcen 1 daisy-chain select input (level sensitive, active high). when high, this signal is used in conjunction with ser/par high to enable serial interface daisy-chain mode. cs parallel interface chip select input (level sensitive, acti ve low). if this pin is low, the device is selected. wr parallel interface write input (edge sensitive). the rising edge of wr is used in conjunction with cs low and the address bus inputs to write to the selected ad5379 registers. db13 to db0 parallel data inputs. the ad5379 can accept a straight 14- bit parallel word on db0 to db13, where db13 is the msb and db0 is the lsb. a0 to a7 parallel address inputs. a7 to a4 are decoded to select one gr oup or multiple groups of registers (input registers, gain registers (m) or offset registers (c)) for a data transfer. this pin is used in conj unction with the reg1 and reg0 pins to determine the destination register for the input data. see the parallel interface section for details of the address decoding. reg0 parallel interface register select input. this pin is used toge ther with reg1 to select data registers, gain registers, offset registers, increment/decrement mode, or the soft reset function. see table 11. clr asynchronous clear input (level sensitive, active low). when clr is low, the input to ea ch of the dac output buffer stages, vout0 to vout39, is switched to the externally set potential on the relevant refgnd pin. while clr is low, all ldac pulses are ignored. when clr is taken high again, the dac outputs remain cl eared until ldac is taken low. the contents of input registers and dac register s 0 to 39 are not affected by taking clr low. busy digital input/open-drain output. this pin must be pulle d high with a pull-up resistor for correct operation. busy goes low during internal calculations of x2. during this time, th e user can continue writing ne w data to additional 1, c, and m registers (these are stored in a fifo), but no furt her updates to the dac regist ers and dac outputs can take place. if ldac is taken low while busy is low, this event is stored. because busy is bidirectional, it can be pulled low externally to delay ldac action. busy also goes low during power-on reset or when the reset pin is low. during a reset operation, the parallel interface is disabled and any events on ldac are ignored. ldac load dac logic input (active low). if ldac is taken low while busy is inactive (high), the contents of the input registers are transferred to the dac register s and the dac outputs are updated. if ldac is taken low while busy is active and internal calculations are taking place, the ldac event is stored and the dac registers are updated when busy goes inactive. however, any events on ldac during power-on reset or reset are ignored. fifoen fifo enable (level sensitive, active high ). when connected to dvdd, the internal fifo is enabled, allowing the user to write to the device at full speed. fifo is available in both serial and parallel mode. the fifoen pin has an internal 1 m? pull-down resistor connected to ground, me aning that the fifo is disabled by default.
ad5379 rev. 0 | page 14 of 28 pin function reset asynchronous digital rese t input (falling edge sensitive). if unused, reset may be left unconnected; an internal pull- up resistor (1 m?) ensures that the reset input is held high. the function of th is pin is equivalent to that of the power-on reset generator. when this pin is taken low, the ad5379 state machine initiates a reset sequence to digitally reset x1, m, c, and x2 registers to their default power-on values. this sequence takes 100 s (typ). furthermore, the input to each of the dac output buffer stages, vout0 to vout39, is switched to the externally set potential on the relevant refgnd pin. during reset , busy goes low and the parallel interface is disabled. all ldac pulses are ignored until busy goes high. when reset is taken high again, the dac ouputs remain at refgnd until ldac is taken low. refgnda1 reference ground for dacs 0 to 7. vo ut0 to vout7 are referenced to this voltage. refgnda2 reference ground for dacs 8 and 9. vo ut8 and vout9 are referenced to this voltage. refgndb1 reference ground for dacs 10 to 17. vo ut10 to vout17 are referenced to this voltage. refgndb2 reference ground for dacs 18 and 19. vout 18 and vout19 are referenced to this voltage. refgndc1 reference ground for dacs 20 to 27. vo ut20 to vout27 are referenced to this voltage. refgndc2 reference ground for dacs 28 and 29. vout 28 and vout29 are referenced to this voltage. refgndd1 reference ground for dacs 30 to 37. vo ut30 to vout37 are referenced to this voltage. refgndd2 reference ground for dacs 38 and 39. vout 38 and vout39 are referenced to this voltage. 1 these serial interface signals do not require separate pins, but share parallel interface pins.
ad5379 rev. 0 | page 15 of 28 terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (lsb). differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. ideally, with all 0s loaded to the dac and m is all 1s, c is 10 0000 0000 0000: vout (zero-scale) = 2.5 v ref ( ?) ? agnd) + refgnd zero-scale error is a measure of the difference between vout (actual) and vout (ideal) expressed in mv. zero-scale error is mainly due to offsets in the output amplifier. full-scale error full-scale error is the error in dac output voltage when all 1s are loaded into the dac register. ideally, with all 1s loaded to the dac and m is all 1s, c is 10 0000 0000 0000: vout (full-scale) = 3.5 ( v ref (+) ? agnd ) + 2.5 ( v ref (?) ? agnd ) + refgnd full-scale error is a measure of the difference between vout (actual) and vout (ideal) expressed in mv. it does not include zero-scale error. gain error gain error is the difference between full-scale error and zero- scale error. it is expressed in mv. gain error = full-scale error ? zero-scale error vout temperature coefficient this includes output error contributions from linearity, offset, and gain drift. dc output impedance dc output impedance is the effective output source resistance. it is dominated by package lead resistance. dc crosstalk the 40 dac outputs are buffered by op amps that share common v dd and v ss power supplies. if the dc load current changes in one channel (due to an update), this can result in a further dc change in one or more channel outputs. this effect is more significant at high load currents and reduces as the load currents are reduced. with high impedance loads, the effect is virtually unmeasurable. multiple v dd and v ss terminals are provided to minimize dc crosstalk. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a full-scale input change. digital-to-analog glitch energy this is the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x1fff and 0x2000. channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from one dacs reference input that appears at the output of another dac operating from another reference. it is expressed in db and measured at midscale. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. it is specified in nv-s. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter is defined as the digital crosstalk and is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density this is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/(hz) 1/2 .
ad5379 rev. 0 | page 16 of 28 typical performance characteristics ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 inl (lsb) 8 6 24 010121416 ad5379 code (10 3 ) 03165-prt-015 v dd = 12v v ss = ?12v v ref (+) = 5v v ref (?) = ?3.5v t a = 25c figure 8. typical inl plot 0 200 400 600 800 1000 1200 1400 frequency ?1 0 ?3 ?2 1 2 3 inl error (lsb) 03165-prt-016 v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v figure 9. inl error distribution (?40c, +25c, +85c superimposed) ?3 ?2 ?1 0 1 2 3 inl error (lsb) ?40 ?20 0 20 40 60 80 temperature (c) 03165-prt-017 v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v t max = +85c figure 10. typical inl error vs. temperature ?4 ?3 ?2 ?1 0 1 2 3 error (mv) 40 20 ?20 0 ?40 60 80 temperature (c) 03165-prt-018 v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v t max = +85c fs zc figure 11. typical full-scale and zero-scale errors vs. temperature 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 19.0 i dd (ma) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 v dd (v) 03165-prt-019 v dd = 12v v ss = ?12v v ref (+) = 5v v ref (?) = ?3.5v ?40c +25c +85c figure 12. i dd vs. v dd over temperature ?15.8 ?15.6 ?15.4 ?15.2 ?15.0 ?14.8 ?14.6 i ss (ma) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 v dd (v) 03165-prt-020 v dd = 12v v ss = ?12v v ref (+) = 5v v ref (?) = ?3.5v ?40c +25c +85c figure 13.i ss vs. v dd over temperature
ad5379 rev. 0 | page 17 of 28 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i cc (ma) 3.5 4.0 2.5 3.0 4.5 5.0 5.5 frequency (mhz) 03165-prt-021 v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v ?40c +25c +85c figure 14. i cc vs. supply ?0.223 ?0.220 ?0.217 ?0.214 ?0.211 ?0.208 amplitude (v) 0 4 8 12 16 20 time ( s) 03165-prt-012 t a = 25c v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v figure 15. major code transition glitch energy ?0.211 ?0.209 ?0.210 ?0.208 amplitude (v) 0 1.4 2.8 4.2 5.6 6.0 time ( s) 03165-prt-013 t a = 25c v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v figure 16. digital feedthrough 03165-prt-014 v out 5mv 10v t a = 25c v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v figure 17. dac-to-dac crosstalk 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 i cc (ma) 1.2 1.6 2.0 2.4 2.8 3.2 0.4 0.8 0 input voltage (v) 03165-prt-027 t a = 25c v dd = +12v v ss = ?12v v ref (+) = +5v v ref (?) = ?3.5v v cc = +3.3v figure 18. supply current vs. digital input voltage
ad5379 rev. 0 | page 18 of 28 functional description dac architecturegeneral the ad5379 contains 40 dac channels and 40 output amplifiers in a single package. the architecture of a single dac channel consists of a 14-bit resistor-string dac followed by an output buffer amplifier. the resistor-string section is simply a string of resistors, each of value r, from v ref (+) to agnd. this type of architecture guarantees dac monotonicity. the 14-bit binary digital code loaded to the dac register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. the output amplifier translates the output of the dac to a wider range. the dac output is gained up by a factor of 3.5 and offset by the voltage on the v ref (?) pin. see the transfer function section. channel groups the 40 dac channels on the ad5379 are arranged into four groups (a, b, c, d) of 10 channels. in each group, eight channels are connected to v ref 1(+) and v ref 1(?) and the remaining two channels are connected to v ref 2(+) and v ref 2(?). each group has two individual refgnd pins. for example, in group a, eight channels are connected to refgnda1, and the remaining two channels are connected to refgnda2. in addition to an input register (x1) and a dac register (x2), each channel has a gain register (m) and an offset register (c). see table 17. the inclusion of these registers allows the user to calibrate out errors in the complete signal chain, including the dac errors. table 9 shows the reference and refgnd inputs, and the m and c registers for group a. groups b, c, and d are similar. table 9. inputs and registers for group a channel reference refgnd m, c registers 07 v ref 1(+), v ref 1(?) refgnda1 m reg07 c reg07 89 v ref 2(+), v ref 2(?) refgnda2 m reg89 c reg89 transfer function the digital input transfer function for each dac can be represented as x2 = [( m + 1)/2 14 x1 ] + ( c ? 2 n?1 ) where: x2 is the data-word loaded to the resistor string dac. (default is 10 0000 0000 0000.) x1 is the 14-bit data-word written to the dac input register. (default is 10 0000 0000 0000.) m is the 13-bit gain coefficient. (default is 1 1111 1111 1111.) c is the 14-bit offset coefficient. (default is 10 0000 0000 0000.) n is the dac resolution. ( n = 14). figure 19 shows a single dac channel and its associated registers. the power-on values for the m and c registers are full scale and 0x2000, respectively. the user can individually adjust the voltage range on each dac channel by overwriting the power-on values of m and c. the ad5379 has digital overflow and underflow detection circuitry to clamp the dac output at full scale or zero scale when the values chosen for x1, m, and c result in x2 being out of range. dac x2 v ref (+) agnd x2 reg x1 input reg dac m reg c reg input data vdac dac reg ldac 03165-prt-008 figure 19. single dac channel the complete transfer function for the ad5379 can be represented as vout = 3.5 (( v ref (+)? agnd ) x2 /2 14 ) + 2.5 ( v ref (?)? agnd ) + refgnd where: x2 is the data word loaded to the resistor string dac. v ref (+) is the voltage at the positive reference pin. v ref (?) is the voltage at the negative reference pin. figure 20 shows the output amplifier stage of a single channel. vdac is the voltage output from the resistor string dac. the nominal range of vdac is 1 lsb to full scale. vdac r r r 2.5r 2.5r vout v ref (?) refgnd agnd 03165-prt-009 figure 20. output amplifier stage
ad5379 rev. 0 | page 19 of 28 v bias function the ad5379 has an on-chip voltage generator that provides a bias voltage of 4.25 v (min). the v bias pin is provided for bypassing and overdriving purposes only. it is not intended to be used as a supply or a reference. if v ref (+) > 4.25 v, v bias must be pulled high externally to an equal or higher potential (such as 5 v). the external voltage source should be capable of driving a 50 a (typical) current sink load. reference selection the voltages applied to v ref (+) and v ref (?) determine the output voltage range and span on vout0 to vout39. if the offset and gain features are not used (m and c are left at their power-on values), the reference levels required can be calculated as follows: v ref (+) min = ( vout max ? vout min )/3.5 v ref (?) max = ( agnd + vout min )/2.5 if the offset and gain features of the ad5379 are used, then the output range required is slightly different. the output range chosen should take into account the offset and gain errors that need to be trimmed out. therefore, the chosen output range should be larger than the actual required range. the reference levels required can be calculated as follows: 1. identify the nominal output range on vout. 2. identify the maximum offset span and the maximum gain required on the full output signal range. 3. calculate the new maximum output range on vout including the maximum offset and gain errors expected. 4. choose the new vout max and vout min required, keeping the new vout limits centered on the nominal values and assuming refgnd is zero (or equal to agnd). note that v dd and v ss must provide sufficient headroom. 5. calculate the values of v ref (+) and v ref (?) as follows: v ref (+) min = ( vout max ? vout min )/3.5 v ref (?) max = ( agnd + vout min )/2.5 in addition, when using reference values other than those suggested (v ref (+) = 5 v and v ref (?) = ?3.5 v), the expected offset error component changes as follows: v offset = 0.125 ( v ref (?) a + 0.7 v ref (+) a ) where: v ref (?) a is the new negative reference value. v ref (+) a is the new positive reference value. if this offset error too large to calibrated out, then it is possible to adjust the negative reference value to account for this using the following equation: v ref (?) new = v ref (?) a ? v offset /2.625 reference selection example nominal output range = 10 v; (?2 v to +8 v) offset error = 100 mv; gain error = 3%; refgnd = agnd = 0 v; 1) gain error = 3%; => maximum positive gain error = +3% => output range incl. gain error = 10 + 0.03 (10) = 10.3 v 2) offset error = 100 mv; => maximum offset error span = 2(100) mv = 0.2 v => output range incl. gain error and offset error = 10.3 + 0.2 = 10.5 v 3) v ref (+) and v ref (?) calculation: actual output range = 10.5 v, that is, ?2.25 v to +8.25 v (centered); => v ref (+) = (8.25 + 2.25)/3.5 = 3 v v ref (?) = ?2.25/2.5 = ?0.9 v if the solution yields inconvenient reference levels, the user can adopt one of three approaches: ? use a resistor divider to divide down a convenient, higher reference level to the required level. ? select convenient reference levels above v ref (+) min or below v ref (?) max . modify the gain and offset registers to downsize the references digitally. in this way, the user can use almost any convenient reference level, but may reduce perform- ance by overcompaction of the transfer function. ? use a combination of these two approaches.
ad5379 rev. 0 | page 20 of 28 calibration the user can perform a system calibration by overwriting the default values in the m and c registers for any individual dac channel as follows: ? calculate the nominal offset and gain coefficients for the new output range (see previous example). ? calculate the new m and c values for each channel based on the specified offset and gain errors. calibration example nominal offset coefficient = 0 nominal gain coefficient = 10/10.5 8191 = 0.95238 8191 = 7801 example 1: channel 0, gain error = 3%, offset error = 100 mv 1) gain error (3%) calibration: 7801 1.03 = 8035 => load code 1 1111 0110 0011 to m register 0 2) offset error (100 mv) calibration: lsb size = 10.5 / 16384 = 641 v; offset coefficient for 100 mv offset = 100 / 0.64 = 156 lsbs => load 10 0000 1001 1100 to c register 0 example 2: channel 1, gain error = ?3%, offset error = ?100 mv 1) gain erro r (?3%) calibration: 7801 0.97 = 7567 => load code 1 1110 1000 1111 to m register 1 2) offset error (?100 mv) calibration: lsb size = 10.5 / 16384 = 641 v; offset coefficient for ?100 mv offset = ?100 / 0.64 = ?156 lsbs => load 01 1111 0110 0100 to c register 1 clear function the clear function on the ad5379 can be implemented in hardware or software. hardware clear bringing the clr pin low switches the outputs, vout0 to vout39, to the externally set potential on the refgnd pin. this is achieved by switching in refgnd and reconfiguring the output amplifier stages into unity gain buffer mode, thus ensuring vout = refgnd. the contents of the input registers and dac registers are not affected by taking clr low. when clr is brought high, the dac outputs remain cleared until ldac is taken low. while clr is low, the value of ldac is ignored. software clear loading a clear code to the x1 registers also enables the user to set vout0 to vout39 to the refgnd level. the default clear code corresponds to m at full scale and c at midscale (x 2 = x 1 ). default clear code = 2 14 (? output offset )/( output range ) = 2 14 2.5 ( agnd ? v ref (?))/(3.5 ( v ref (+)? agnd )) the more general expression for the clear code is as follows: clear code = (2 14 )/( m + 1) ( default clear code ? c ) busy and ldac functions the value of x2 is calculated each time the user writes new data to the corresponding x1, c, or m registers. during the calcula- tion of x2, the busy output goes low. while busy is low, the user can continue writing new data to the x1, m, or c registers, but no dac output updates can take place. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs update immediately after busy goes high. a user can also hold the ldac input permanently low. in this case, the dac outputs update immediately after busy goes high. table 10. busy pulse width busy pulse width (ns max) action fifo enabled fifo disabled loading x1, c, or m to 1 channel 530 330 loading x1, c, or m to 2 channels 700 500 loading x1, c, or m to 3 channels 900 700 loading x1, c, or m to 4 channels 1050 850 loading x1, c, or m to all 40 channels 5500 5300 the value of x2 for a single channel or group of channels is recalculated each time there is a write to any x1 register(s), c register(s), or m register(s). during the calculation of x2, busy goes low. the duration of this busy pulse depends on the number of channels being updated. for example, if x1, c, or m data is written to one dac channel, busy goes low for 550 ns (max). however, if data is written to two dac channels, busy goes low for 700 ns (max). note that there are approximately 200 ns of overhead due to fifo access. see table 10. the ad5379 contains an extra feature whereby a dac register is not updated unless its x2 register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2 registers. however the ad5379 updates the dac register only if the x2 data has changed, thereby removing unnecessary digital crosstalk.
ad5379 rev. 0 | page 21 of 28 fifo vs. non-fifo operation two modes of operation are available for loading data to the ad5379 registers: operation with fifo disabled and operation with fifo enabled. operation with fifo disabled is optimum for single writes to the device. if the system requires significant data transfers to the ad5379, however, then operation with fifo enabled is more efficient. when fifo is enabled, the ad5379 uses an internal fifo memory to allow high speed successive writes in both serial and parallel modes. this optimizes the interface speed and efficiency, minimizes the total conversion time due to internal digital efficiencies, and minimizes the overhead on the master controller when managing the data transfers. the busy signal goes low while instructions in the state machine are being executed. table 10 compares operation with fifo enabled and fifo disabled for different data transfers to the ad5379. operation with fifo enabled is more efficient for all operations except single write operations. when using the fifo, the user can continue writing new data to the ad5379 while write instruc- tions are being executed. up to 128 successive instructions can be written to the fifo at maximum speed. when the fifo is full, additional writes to the ad5379 are ignored. busy input function because the busy pin is bidirectional and open-drain (for correct operation, use pull-up resistor to digital supply), a second ad5379 or any other device (such as a system control- ler), can pull busy low and, therefore, delay dac update(s), if required. this is a means of delaying any ldac action. this feature allows synchronous updates of multiple ad5379 devices in a system at maximum speed. as soon as the last device connected to the busy pin is ready, all dacs update automatically. tying the busy pin of multiple devices together enables synchronous updating of all dacs without extra hardware. power-on reset function the ad5379 contains a power-on reset generator and state machine. during power-on, clr becomes active (internally), the power-on state machine resets all internal registers to their default values, and busy goes low. this sequence takes 8 ms (typical). the outputs, vout0 to vout39, are switched to the externally set potential on the refgnd pin. during power-on, the parallel interface is disabled, so it is not possible to write to the part. any transitions on ldac during the power-on period are ignored in order to reject initial ldac pin glitching. a rising edge on busy indicates that power-on is complete and that the parallel interface is enabled. all dacs remain in their power-on state until ldac is used to update the dac outputs. reset input function the ad5379 can be placed in its power-on reset state at any time by activating the reset pin. the ad5379 state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. this sequence takes 95 s (typical), 120 s (max), 70 s (min). during this sequence, busy goes low. while reset is low, any transitions on ldac are ignored. as with the clr input, while reset is low, the dac outputs are switched to refgnd. the outputs remain at refgnd until an ldac pulse is applied. this reset function can also be implemented via the parallel interface by setting the reg0 and reg1 pins low and writing all 1s to db13 to db0 (see table 16 for soft reset). increment/decrement function the ad5379 has a special function register that enables the user to increment or decrement the internal 14-bit input register data (x1) in steps of 0 to 127 lsbs. the increment/decrement function is selected by setting both reg1 and reg0 pins (or bits) low. address pins (or bits) a7 to a0 are used to select a dac channel or group of channels. the amount by which the x1 register is incremented or decremented is determined by the db6 to db0 bits/pins. for example, for a 1 lsb increment or decrement, db6...db0 = 0000001, while for a 7 lsb increment or decrement, db6...db0 = 0000111. db8 determines whether the input register data is incremented (db8 = 1) or decre- mented (db8 = 0). the maximum amount by which the user is allowed to increment or decrement the data is 127 lsbs, that is, db6...db0 = 1111111. the 0 lsb step is included to facilitate software loops in the users application. see table 15. the ad5379 has digital overflow and underflow detection circuitry to clamp at full scale or zero scale when the values chosen for increment or decrement mode are out of range.
ad5379 rev. 0 | page 22 of 28 interfaces the ad5379 contains a parallel and a serial interface. the active interface is selected via the ser/ par pin. the ad5379 uses an internal fifo memory to allow high speed successive writes in both serial and parallel mode. the user can continue writing new data to the ad5379 while write instruc- tions are being executed. the busy signal goes low while instructions in the fifo are being executed. up to 120 succes- sive instructions can be written to the fifo at maximum speed. when the fifo is full, additional writes to the ad5379 are ignored. to minimize both the power consumption of the device and on-chip digital noise, the active interface powers up fully only when the device is being written to, that is, on the falling edge of wr or on the falling edge of sync . all digital interfaces are 2.5 v lvttl compatible when operating from a 2.7 v to 3.6 v v cc supply. parallel interface a pull-down on the ser/ par pin makes the parallel interface the default. if using the parallel interface, the ser/ par pin can be left unconnected. figure 6 shows the timing diagram for a parallel write to the ad5379. the parallel interface is controlled by the following pins. cs pin active low device select pin. wr pin on the rising edge of wr , with cs low, the address values at pins a7 to a0 are latched and data values at pins db13 to db0 are loaded into the selected ad5379 input registers. reg1, reg0 pins the reg1 and reg0 pins determine the destination register of the data being written to the ad5379. see table 11. table 11. register selection reg1 reg0 register selected 1 1 input data register (x1) 1 0 offset register (c) 0 1 gain register (m) 0 0 special function register db13 to db0 pins the ad5379 accepts a straight 14-bit parallel word on db0 to db13, where db13 is the msb and db0 is the lsb. see table 12, table 13, table 14, table 15, and table 16. a7 to a0 pins each of the 40 dac channels can be addressed individually. in addition, several channel groupings enable the user to simulta- neously write the same data to multiple dac channels. address bits a7 to a4 are decoded to select one group or multiple groups of registers. address bits a3 to a0 select one of ten input data registers (x1), offset register s (c), or gain registers (m). see table 17. serial interface the ser/ par pin must be tied high to enable the serial inter- face and disable the parallel interface. the serial interface is controlled by five pins, as follows. sync , din, sclk standard 3-wire interface pins. dcen selects standalone mode or daisy-chain mode. sdo data out pin for daisy-chain mode. figure 4 and figure 5 show the timing diagrams for a serial write to the ad5379 in standalone and daisy-chain modes, respectively. the 24-bit data word format for the serial interface is shown in figure 21. msb reg0 db13?db0 lsb a7?a0 reg1 register data bits group/channel select bits register select bits 03165-prt-024 figure 21. serial data format standalone mode by connecting the dcen (daisy-chain enable) pin low, standalone mode is enabled. the serial interface works with both a continuous and a burst serial clock. the first falling edge of sync starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits is shifted into the serial shift register. additional edges on sync are ignored until 24 bits are shifted in. once 24 bits are shifted in, the sclk is ignored. in order for another serial transfer to take place, the counter must be reset by the falling edge of sync .
ad5379 rev. 0 | page 23 of 28 daisy-chain mode for systems that contain several dacs, the sdo pin can be used to daisy-chain several devices together. this daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. connecting the dcen (daisy-chain enable) pin high enables daisy-chain mode. the first falling edge of sync starts the write cycle. the sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the din input on the next device in the chain, a multidevice interface is constructed. for each ad5379 in the system, 24 clock pulses are required. therefore, the total number of clock cycles must equal 24 n , where n is the total number of ad5379 devices in the chain. if fewer than 24 clocks are applied, the write sequence is ignored. when the serial transfer to all devices is complete, sync should be taken high. this latches the in put data in each device in the daisy chain and prevents any additional data from being clocked into the input shift register. a continuous sclk source can be used, if sync is held low for the correct number of clock cycles. alternatively, a burst clock containing the exact number of clock cycles can be used and sync taken high after the final clock to latch the data. when the transfer to all input registers is complete, a common ldac signal updates all dac registers, and all analog outputs are updated simultaneously.
ad5379 rev. 0 | page 24 of 28 data decoding the ad5379 contains a 14-bit data bus, db13 to db0. depend- ing on the value of reg1 and reg0, this data is loaded into the addressed dac input register(s), offset (c) register(s), gain (m) register(s), or the special function register. table 12. dac data format (reg1 = 1, reg0 = 1) db13 to db0 dac output 11 1111 1111 1111 (16383/16384) v ref (+) v 11 1111 1111 1110 (16382/16384) v ref (+) v 10 0000 0000 0001 (8193/16384) v ref (+) v 10 0000 0000 0000 (8192/16384) v ref (+) v 01 1111 1111 1111 (8191/16384) v ref (+) v 00 0000 0000 0001 (1/16384) v ref (+) v 00 0000 0000 0000 0 v table 13. offset data format (reg1 = 1, reg0 = 0) db13 to db0 offset (lsb) 11 1111 1111 1111 +8191 11 1111 1111 1110 +8190 10 0000 0000 0001 +1 10 0000 0000 0000 +0 01 1111 1111 1111 ?1 00 0000 0000 0001 ?8191 00 0000 0000 0000 ?8192 table 14. gain data format (reg1 = 0, reg0 = 1) db12 to db1 gain 1 1111 1111 1111 8192/8192 1 1111 1111 1110 8191/8192 1 0000 0000 0001 4098/8192 1 0000 0000 0000 4097/8192 0 1111 1111 1111 4096/8192 0 0000 0000 0001 2/8192 0 0000 0000 0000 1/8192 table 15. special function data format (reg1 = 0, reg0 = 0) db13 to db0 increment/ decrement step (lsb) 00000 10 1111111 +127 00000 10 0000111 +7 00000 10 0000001 +1 00000 x0 0000000 0 00000 00 0000001 ?1 00000 00 0000111 ?7 00000 00 1111111 ?128 table 16. soft reset (reg1 = 0, reg0 = 0) db13 to db0 dac output 11 1111 1111 1111 refgnd
ad5379 rev. 0 | page 25 of 28 address decoding the ad5379 contains an 8-bit address bus, a7 to a0. this address bus allows each dac input register (x1), each offset (c) register, and each gain (m) register to be individually updated. the reg1 and reg0 bits in the special function register (sfr) (see table 9) show the decoding for data, offset, and gain registers. note that when all 40 dac channels are selected, address bits a[3:0] are ignored. table 17. dac group addressing a7 a6 a5 a4 group a3 a2 a1 a0 data/offset/gain/inc-dec register 0 0 0 0 all 40 dacs 0 0 0 0 register 0 0 0 0 1 group 1 0 0 0 1 register 1 0 0 1 0 group 2 0 0 1 0 register 2 0 0 1 1 groups 1, 2 0 0 1 1 register 3 0 1 0 0 group 3 0 1 0 0 register 4 0 1 0 1 groups 1, 3 0 1 0 1 register 5 0 1 1 0 groups 2, 3 0 1 1 0 register 6 0 1 1 1 groups 1, 2, 3 0 1 1 1 register 7 1 0 0 0 group 4 1 0 0 0 register 8 1 0 0 1 groups 1, 4 1 0 0 1 register 9 1 0 1 0 groups 2, 4 1 0 1 1 groups 1, 2, 4 1 1 0 0 groups 3, 4 1 1 0 1 groups 1, 3, 4 1 1 1 0 groups 2, 3, 4 1 1 1 1 groups 1, 2, 3, 4
ad5379 rev. 0 | page 26 of 28 power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5379 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5379 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (v ss , v dd , v cc ), it is recom- mended to tie these pins together and to decouple each supply once. the ad5379 should have ample supply decoupling of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capaci- tor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. digital lines running under the device should be avoided, because these couple noise onto the device. the analog ground plane should be allowed to run under the ad5379 to avoid noise coupling. the power supply lines of the ad5379 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. it is essential to mini- mize noise on all v ref (+) and v ref (?) lines. the v bias pin should be decoupled with a 10 nf capacitor to agnd. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the cspbga package and to avoid a point load on the surface of this package during the assembly process. power-on an on-chip power supply monitor makes the ad5379 robust to power sequencing. the supply monitor powers up the analog section after (v dd ? v ss ) is greater than 7 v (typical). the output buffers power up in clr mode forced to the dutgnd potential, even if v cc remains at 0 v. after v ss is applied, the analog circuitry powers up and the buffered dac output level settles linearly within the supply range.
ad5379 rev. 0 | page 27 of 28 typical application circuit the high channel count of the ad5379 makes it well suited to applications requiring high levels of integration such as optical and automatic test equipment (ate) systems. figure 22 shows the ad5379 as it would be used in an ate system. shown here is one pin of a typical logic tester. it is apparent that a number of discrete levels are required for the pin driver, active load circuit, parametric measurement unit, comparators, and clamps. in addition to the dac levels required in the ate system shown, drivers, loads, comparators, and parametric measurement unit functions are also required. analog devices provides solutions for all these functions. dac central pmu driven shield v ch v th v tl i ol v com i oh v cl v h v l driver comp active load formatter de-skew compare memory timing data memory timing generator dll logic formatter de-skew v term ppmu relays gnd sense device power supply 50 ? coax dut guard amp dac dac dac dac dac dac dac dac dac dac adc dac adc dac adc 03165-prt-011 figure 22. typical application circuit for logic tester
ad5379 rev. 0 | page 28 of 28 outline dimensions b c d e f g h j k l m a seating plane detail a 0.75 0.70 0.65 ball diameter 0.12 max coplanarity 1.00 bsc 0.64 typ 11.00 bsc 12 11 10 9 8 7 6 5 4 3 2 1 1.05 1.00 0.90 a1 corner index area *1.85 1.70 1.55 top view bottom view 13.00 bsc sq ball a1 indicator detail a *compliant with jedec standards mo-192-aad-1 except for package height (dimension a). figure 23. 108-lead chip scale ball grid array [cspbga] (bc-108) dimensions shown in millimeters ordering guide model temperature range linearity error (l sbs) package description package option ad5379abc ?40c to +85c 3 108-lead cspbga bc-108 EVAL-AD5379EB evaluation board and software ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03165C0C4/04(0)

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